Input and output is performed using access to coprocessor #3, denoted in source code by p3. There are three valid access types, and each accesses a different set of registers.

All usage of CP3 requires privilege, i.e. CP3 instructions are Undefined in User mode.

Memory Transfer

This covers the LDC and STC instructions that respectively load and store registers directly from and to memory. The normal set of indexing combinations for a load/store are available.

LDC p3, cr1, [r2]            // Read memory starting at r2 into register cr1
STC p3, cr1, [r2]            // Write the register cr1 to memory starting at r2

Registers

Core Register Transfer

This covers the MRC and MCR instructions that (respectively) read and write coprocessor registers to and from core registers.

MRC p3, X, r1, cr2, cr3      // r1 := value of register cr2, cr3
MCR p3, X, r1, cr2, cr3      // register cr2, cr3 := value of r1
                             // (X is ignored in both cases and should be 0)

Registers

Multiple Core Register Transfer

This covers the MRRC and MCRR instructions that (respectively) read and write coprocessor registers to and from two core registers.

MRRC p3, X, r1, r2, cr3     // r1 (low), r2 (high) := value of register cr3
MCRR p3, X, r1, r2, cr3     // register cr3 := value of r1 (low), r2 (high)
                            // (X is ignored in both cases and should be 0)

Operations

Covers the CDP instruction, and therefore all operations that are neither logical loads/stores of coprocessor registers nor transfers between them and core registers.

Interchange Buffers

Interchange buffers are used to exchange data between OpenComputers devices and the ARM processor. There are two formats depending on the value of the Interchange Control Register: the default unpacked format is alignment friendly, and significantly faster when using 32-bit memory; the packed format requires relaxed alignment and is significantly slower using 32-bit memory, but not too much slower using 16-bit memory, and somewhat smaller.

Interchange Value

An Interchange Value is a type tag, followed by its data. In unpacked format, the tag is a 32-bit word; in packed format, it is a 16-bit halfword.

Interchange Buffer

An interchange buffer consists of a series of values, like an implicit ICTAG_ARRAY. In most cases (Invoke and signals), an interchange buffer should contain a ICTAG_STRING as its first element. Reply Buffers have a 32-bit (or 16-bit if packed) result code before its first element, containing one of the following codes:

Serial Debug Coprocessor

If the allowSerialDebugCP option is enabled in mcjarm.cfg, the following unprivileged operations are also possible: